The present invention generally pertains to ratio-matched networks contained in a circuit chip, and is particularly directed to maximizing the accuracy of such networks within a given die area.
The present invention is applicable to both ratio-matched resistance networks and ratio-matched capacitance networks. A ratio-matched resistance network consists of a plurality of resistances having a rational ratio of resistance values to each other. A rational ratio is a ratio defined by a rational number. A ratio-matched capacitance network consists of a plurality of capacitances having a rational ratio of capacitance values to each other.
When a ratio-matched resistance network is included in a circuit chip, all of the resistances each consists of an integral number of simultaneously fabricated resistors of approximately uniform dimensions.
Ratio-matched resistance networks are commonly used as attenuators in signal generators, digital to analog (D/A) and analog to digital (A/D) converters, and other devices where voltages and currents must be reduced in known ratios. In integrated circuit D/A and A/D converters, an R-2R resistance ladder network is contained in a monolithic circuit chip.
A prior art ten-bit R-2R resistance ladder network is shown in FIG. 1. Such network includes a voltage reference terminal V.sub.REF ; nine resistance branches 10 through 18 connected in series to the voltage reference terminal V.sub.REF, with each branch having a given resistance R; and eleven resistance legs 20 through 30 respectively connected to ends of each series resistance branch, with each leg having a resistance 2R. The legs 29 and 30 are connected in parallel at the end of the series resistance branch 18 that is the most remote from the voltage reference terminal V.sub.REF. All of the resistances consist of one or more resistors. All of the resistors have a common nominal resistance R.sub.o with a standard deviation of .sigma., whereby the spread of resistance values is 2.sigma..
The accuracy of an R-2R resistance ladder network is determined by the matching accuracy of the component resistors.
During the manufacture of matched resistors on a chip, a distribution of resistor values is obtained. Their distribution has a mean value R.sub.o and a spread of values 2.sigma.. FIG. 2 shows a resistance value distribution for a single connected resistor, as shown in FIG. 2A. The accuracy of the rational ratio of the resistances to each other can be enhanced by increasing the die area of each resistor. However, this would undesirably increase the total die area of the resistance ladder network, and thereby necessitate fabrication of a larger chip.
When a ratio-matched capacitance network is included in a circuit chip, all of the capicitances each consists of an integral member of simultaneously fabricated capacitors of approximately uniform dimensions. In contrast to a typical prior art ratio-matched resistance network wherein a resistance having a value of 2R consists of a pair of resistors of nominal value R.sub.o connected in series with each other, in a typical prior art ratio-matched capacitance network, a capacitance having a value of 2C consists of a pair of capacitors of a nominal value C.sub.o connected in parallel with each other. In respect to the relationship between the size of the die area of each capacitor and the accuracy of the rational ratio of the capacitances to each other, the same considerations prevail as for the ratio-matched resistance network in a circuit chip discussed hereinabove.